Method for fabricating semiconductor packages, and structure and method for positioning semiconductor components

ABSTRACT

A method for fabricating semiconductor packages includes the steps of: providing a plurality of substrates and a carrier having a plurality of openings, wherein, each of the substrates has at least one chip (die) disposed thereon, length and width of the substrates are approximately equal to the predefined length and width of semiconductor packages, and length and width of the openings of the carrier are bigger than length and width of the substrates; respectively positioning the substrates in the openings of the carrier and blocking the gaps between the substrates and the carrier so as to prevent the gaps from penetrating through the carrier; performing a mold press process so as to form an encapsulant on each of the openings for encapsulating the chip, wherein length and width of the area covered by the encapsulant are bigger than length and width of the opening; performing a mold releasing process; and cutting along edges of the substrates according to the predefined length and width of semiconductor packages, thereby obtaining a plurality of semiconductor packages. The present invention also discloses a structure and method for positioning the substrates.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation-in-part of copending application Ser. No. 11/117,158 filed on Apr. 27, 2005, the disclosure of which is expressly incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a method for fabricating semiconductor packages, and more particularly to a method for fabricating BGA semiconductor packages by using a substrate carrier, and a structure and method for positioning semiconductor components.

2. Description of Related Art

A flip-chip ball grid array (FCBGA) semiconductor package integrates both a flip-chip structure and a ball grid array (BGA) structure, wherein an active surface of at least one chip (die) is electrically connected to one surface of a substrate through a plurality of solder bumps, and a plurality of solder balls functioning as I/O terminals is mounted on the other surface of the substrate. Such a package structure not only decreases the package volume, but also eliminates the need for a wires bonding, which accordingly decreases resistance and improves the electrical characteristics of the whole structure. As a result, the signal fading phenomenon that occurs in the signal transfer process can be prevented. Therefore, the FCBGA package structure has become a mainstream packaging technology for next generation chips and electronic components.

FIG. 10 shows a BGA semiconductor package, which comprises a substrate 70, a chip 71 flip-chip electrically connected to an upper surface of the substrate 70, and a plurality of solder balls 72 mounted to a lower surface of the substrate 70 for electrically connecting the chip 71 to the outside. The semiconductor package further comprises an encapsulant 73 formed on the upper surface of the substrate 70 through a mold press process and encapsulating the chip 71. U.S. Pat. No. 6,038,136, 6,444,498, 6,699,731 and Taiwan Patent Publication No. 559,960 disclose similar structures.

FIG. 11 shows a package structure disclosed by Taiwan Patent Publication No. 559960. As shown in FIG. 11, since clamp areas are extended from edges of a substrate 70, the substrate 70 is larger in terms of area than the area of the base of the mold cavity 81 of the encapsulating mold 80. As a result, the substrate 70 can be clamped by the mold 80, thereby preventing the encapsulant 73 from overflowing to the back side of the substrate 70 and protecting solderability of the ball pads 74 on which solder balls not shown are to be mounted. However, such a design increases the size of the substrate 70. For example, for a semiconductor package having a substrate 70 of 31 mm×31 mm as shown in FIG. 10, to obtain good overflow protection efficiency, the width of the clamp area should at least be 0.6 mm. Therefore, both the length and width of the substrate 70 need to be increased by 1.2 mm, which thus increases the substrate material and fabrication cost, as well as the overall package size. Generally, the cost of a flip chip substrate is above 60% of the whole package cost.

Further, to facilitate the mold releasing process, as shown in FIG. 12, a mold releasing angle 82 needs to be formed at the edges of the encapsulant 73 according to the shape of the mold 80, which is generally no larger than 60°. As a result, the encapsulant 73 with the releasing angle 82 should at least correspond to an additional substrate size b of 0.58 mm, which thus increases both length and width of the substrate 70 by 1.16 mm. In addition, a cutting width c of 0.3 mm should be predefined at each side of the substrate 70. Therefore, the size of the substrate 70 should be (31+1.2+1.16+0.6)mm*(31+1.2+1.16+0.6)mm, which not only reduces substrate utilization, but also increases the fabrication cost by about 15˜20%.

Therefore, there is a need to develop a method for fabricating semiconductor packages that can overcome the overflow problem and facilitate the mold releasing process without the need of increasing substrate size.

SUMMARY OF THE INVENTION

According to the above drawbacks, an objective of the present invention is to provide a method for fabricating semiconductor packages that can reduce substrate cost.

Another objective of the present invention is to provide a method for fabricating semiconductor packages without the need of increasing length and width of the substrates.

A further objective of the present invention is to provide a method for fabricating semiconductor packages that can overcome the overflow problem without the need of increasing substrate size.

In order to attain the above and other objectives, the present invention discloses a method for fabricating semiconductor packages, which comprises the steps of: preparing a plurality of substrates and a carrier having a plurality of openings, wherein, each of the substrates has at least one chip (die) disposed thereon, the length and width of the substrates are close to the predefined length and width of the semiconductor packages, and the length and width of the openings of the carrier are bigger than the length and width of the substrates; respectively positioning the substrates in the openings of the carrier and blocking the gaps between the substrates and the carrier so as to prevent the gaps from penetrating through the carrier; performing a mold press process so as to form an encapsulant on each of the openings for encapsulating the chip, wherein the length and width of the area covered by the encapsulant are bigger than the length and width of the opening; performing a mold releasing process; and cutting along edges of the substrates according to the predefined length and width of semiconductor packages, thereby obtaining a plurality of semiconductor packages.

The present invention can position the substrates in the openings and block the gaps between the substrates and the carrier by filling an adhesive material such as a solder mask in the gaps between the substrates and the carrier. Alternatively, at least one tape can be attached to the substrates and the carrier, positioning the substrates and blocking the gaps. To ensure that the adhesive material is sufficiently filled in the gaps between the substrates and the carrier, at least one storage hole is disposed at the periphery of the openings. The adhesive material is first filled in the storage hole through a dispensing method, and then by a capillary effect, the adhesive material is further filled in the gaps. Such a method not only simply positions the substrate in the opening, but also prevents the conventional problems such as substrate shift, uneven adhesive material distribution, interface delamination caused by gaps that are too large, and problems such as slow dispensing speed and increased fabrication cost caused by gaps that are too small.

The length and width of the substrates can be 0.1 to 0.5 mm bigger than the predefined length and width of the semiconductor packages. When the length and width of the substrates are 0.1 to 0.5 mm bigger than the predefined length and width of the semiconductor packages, the length and width of the openings can be 0.1 to 0.5 mm bigger than the length and width of the substrates. On the other hand, the length and width of the substrates can be 0.1 to 0.5 mm smaller than the predefined length and width of the semiconductor packages. When the length and width of the substrates are 0.1 to 0.5 mm smaller than the predefined length and width of the semiconductor packages, the length and width of the openings can be 0.1 to 1 mm bigger than predefined length and width of the semiconductor packages.

The carrier can be made of an organic dielectric material such as FR4, FR5 and BT. The carrier can also be made of a metallic material. The method for fabricating semiconductor packages using a metallic carrier comprises the steps of: preparing a plurality of substrates and a metallic carrier having a plurality of openings, wherein, each of the substrates has at least one chip disposed thereon, the length and width of the substrates being close to the predefined length and width of semiconductor packages, and the length and width of the openings of the carrier being bigger than length and width of the substrates; respectively positioning the substrates in the openings of the metallic carrier and blocking the gaps between the substrates and the metallic carrier so as to prevent the gaps from penetrating through the metallic carrier; performing a mold press process so as to form an encapsulant on each of the openings for encapsulating the chip, thus forming a package unit comprising the substrate, chip and encapsulant, wherein the length and width of the area covered by the encapsulant are bigger than the length and width of the opening; performing a mold releasing process; separating the package units from the metallic carrier; and cutting along edges of the substrates of the package units according to the predefined length and width of semiconductor packages, thereby obtaining a plurality of semiconductor packages.

The metallic carrier is made of Cu, and a metal plated layer having poor adhesion with the encapsulant is formed on the metallic carrier. The metal plated layer can be made of such as Au, Ni and Cr. Through the poor adhesion between the metal plated layer and the encapsulant, the package units can easily be separated from the metallic carrier, thereby facilitating the fabrication process.

The present invention further discloses a method for positioning a semiconductor component. The method includes: providing a semiconductor component and a carrier having an opening, the opening having a length and width bigger than another length and width of the semiconductor component, at least one storage hole being disposed at a periphery of the opening of the carrier; disposing the semiconductor component in the opening of the carrier; and filling in the storage hole an adhesive material, which is filled in the gaps between the semiconductor component and the carrier through a capillary effect, thus positioning the semiconductor component in the carrier. The semiconductor component is, for example, a substrate.

The present invention further discloses a carrier structure for positioning a semiconductor component. The carrier structure includes: a carrier having an opening for receiving the semiconductor component; and at least a storage hole disposed at a periphery of the opening of the carrier such that an adhesive material can be filled in the storage hole, wherein the adhesive material, through the capillary effect, can be filled in the gaps between the semiconductor component and the carrier, thereby positioning the semiconductor component in the carrier.

According to the present invention, the length and width of the substrates are approximately equal to predefined length and width of the semiconductor package. As the gaps between the substrates and the carrier are all blocked and the projection length and width of the mold cavities for forming the encapsulants are designed to be bigger than the length and width of the openings, the overflow problem is solved and the mold releasing process is facilitated without the need of increasing the substrate size, thereby preventing the waste of substrate material, decreasing material costs and simplifying the fabrication process.

The present invention also discloses a method for positioning a semiconductor component such as a substrate in a carrier while blocking the gaps between the semiconductor component and the carrier, which comprises the step of filling an adhesive material in the storage holes disposed at the periphery of the opening of the carrier. Through the capillary effect, the adhesive material is further filled in the gaps between the semiconductor component and the carrier. Thus, the semiconductor component is simply positioned in the opening of the carrier. As the adhesive material is filled in the gaps through the capillary effect, problems such as semiconductor component shift, uneven adhesive material distribution and interface delamination caused by much bigger gaps can be prevented. Moreover, such problems as too slow of a dispensing speed and increased fabrication costs caused by small gaps that are too small are also avoided.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1A to 1H show a method for fabricating semiconductor packages according to a first embodiment of the present invention;

FIG. 2 shows a method for blocking the gaps between the substrates and the carrier;

FIG. 3 shows another method for blocking the gaps between the substrates and the carrier;

FIGS. 4A to 4H show a method for fabricating semiconductor packages according to a second embodiment of the present invention;

FIGS. 5A to 5I show a method for fabricating semiconductor packages according to a third embodiment of the present invention;

FIG. 6 is a sectional diagram of a semiconductor package according to a fourth embodiment of the present invention;

FIG. 7 is a sectional diagram of a semiconductor package according to a fifth embodiment of the present invention;

FIG. 8 is a sectional diagram of a semiconductor package according to a sixth embodiment of the present invention;

FIG. 9 is a sectional diagram of a semiconductor package according to a seventh embodiment of the present invention;

FIG. 10 is a sectional diagram of a conventional BGA semiconductor package;

FIGS. 11 and 12 are diagrams showing a conventional BGA semiconductor package that requires the substrate size to be increased for a mold press process;

FIGS. 13A and 13B are sectional diagrams showing problems generated by substrate shift when the gaps between the substrate and the carrier are too big;

FIGS. 14A to 14C are diagrams showing a method for positioning the substrate in the opening and blocking the gaps between the substrate and the opening according to an eighth embodiment of the present invention; and

FIGS. 15A to 15C are top views of a carrier with storage holes disposed at different positions.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The following illustrative embodiments are provided to illustrate the disclosure of the present invention; these and other advantages and effects can be apparent to those skilled in the art after reading the disclosure of this specification. The present invention can also be performed or applied by other differing embodiments. The details of the specification may be changed on the basis of different points and applications, and numerous modifications and variations can be made without departing from the spirit of the present invention.

First Embodiment

FIGS. 1A to 1H are diagrams showing a method for fabricating semiconductor packages according to a first embodiment of the present invention. As shown in FIG. 1A, a build-up substrate 10 carrying a chip 20 is prepared. The structure is representative of what in application would likely be a plurality of such units, and, hereinafter, reference will be made to such a plurality of such units. The length and width of the substrates 10 are slightly bigger than the predefined length and width of semiconductor packages 1. In the present embodiment, the predefined length and width of semiconductor packages 1 are 31 mm×31 mm, and the length and width of the substrates 10 are 31.4 mm×31.4 mm. Then, a substrate carrier having a plurality of openings is prepared. FIG. 1B shows a portion of such a substrate carrier 15 with an opening 16. The length and width of the openings 16 are bigger than the length and width of the substrates 10 such that the substrates 10 carrying the chips 20 can be correspondingly embedded and positioned in the openings 16. In the present embodiment, the length and width of the openings 16 are designed to be 31.5 mm×31.5 mm. As shown in FIG. 1C, the substrates 10 are positioned in the openings 16 of the carrier 15 and gaps 17 between the substrates 10 and the carrier 15 are blocked so as to prevent the gaps 17 from penetrating through the carrier 15. In the present embodiment, a tape 25 is attached to the lower surfaces of the substrates 10 and the carrier 15 for positioning the substrates 10 and for also covering the gaps 17. The tape 25 may be made of a polymer material that can endure high temperature.

Subsequently, as shown in FIG. 1D, a conventional mold press process is performed, wherein the carrier 15 is disposed in a mold 30 with the chips 20 being accommodated inside corresponding mold cavities 31, and an encapsulant 32 is formed in each of the openings 16 for encapsulating the chips 20. The present invention is characterized in that the substrates 10 having a size of 31.4 mm×31.4 mm are slightly bigger than semiconductor packages 1 having a size of 31 mm×31 mm, and the openings 16 having a size of 31.5 mm×31.5 mm are slightly bigger than the substrates 10 having a size of 31.4 mm×31.4 mm. Moreover, as shown in FIG. 1D, the area covered by the encapsulant 32 is much bigger than length and width of the opening 16. Thus, although the encapsulants 32 injected into the mold cavities 31 can be overflowed into the gaps 17 between the substrates 10 and the carrier 15, the tape 25 can prevent the encapsulants 32 from overflowing to the lower surfaces of the substrates 10. As a result, the size of the substrates 10 does not need to be increased for preventing overflow of the encapsulant. Moreover, as the mold-releasing angle of the encapsulants 32 corresponds to a carrier region instead of a substrate region, the size of the substrates 10 does not need to be increased for facilitating the releasing of the mold 30. Therefore, the fabrication cost of semiconductor packages 1 is decreased.

As shown in FIG. 1E, a mold releasing process is performed and the tape 25 is removed. As shown in FIG. 1F, a plurality of solder balls 18 is mounted to ball pads 19 on the lower surfaces of the substrates 10 where the chips 20 are not mounted such that the chips 20 can be electrically connected to the outside through the solder balls 18. As shown in FIG. 1G, a cutting process is performed along cutting lines of the substrates 10 according to the predefined size of semiconductor packages 1. In the present embodiment, as the predefined size of semiconductor packages 1 is 31 mm×31 mm and the size of the substrates 10 is 31.4 mm×31.4 mm, the substrates 10 have redundant edges with a width of 0.2 mm, which can be cut away by the cutting process as the redundant edges are located in the cutting path with a width of 0.3 mm. Compared with the prior art of FIG. 12 that needs to leave redundant edge material with a width of 1.18 mm (0.6 mm +0.58 mm, excluding a cutting path with a width of 0.3 mm) for the substrate 70, the present invention greatly decreases the use of substrate material. As shown in FIG. 1H, a plurality of semiconductor packages 1 with low cost is obtained.

As described above, the present invention is characterized in that the gaps 17 between the substrate 10 and the carrier 15 are blocked to prevent the overflow of encapsulant 32, and, moreover, the size of the mold cavities 31 for forming the encapsulant 32 is made bigger than that of the openings 16 for facilitating the mold releasing process. Thus, the need for increasing the size of the substrates 10 in order to solve the overflow problem and facilitate the mold releasing process, as in the prior art, is eliminated. Instead, the size of the substrates 10 only needs to be approximately equal to the predefined size of the semiconductor packages 1, thereby decreasing the waste of substrate material.

However, the size of the substrates 10 is not limited to 31.4 mm×31.4 mm. The length and width of the substrates 10 can be 0.1 to 0.5 mm bigger than the predefined length and width of the semiconductor packages 1. Moreover, the size of the openings 16 is not limited to 31.5 mm×31.5 mm. Instead, the length and width of the openings 16 can be 0.1 mm to 0.5 mm bigger than the length and width of the substrates 10. The carrier 15 may be made of an organic dielectric material such as FR4, FR5 and BT.

Furthermore, there are several other methods for positioning the substrates 10 in the openings 16 of the carrier 15 and blocking the gaps 17 between the substrates 10 and the carrier 15 instead of using the tape 25. As shown in FIG. 2, many small sized tapes 40 can be used to cover the gaps 17 between the substrates 10 and the carrier 15 so as to decrease the use of the tape material. The small sized tapes 40 can also be removed after the mold releasing process. In addition, as shown in FIG. 3, an adhesive material 41 such as a solder mask can be filled in the gaps 17 between the substrates 10 and the carrier 15 through a dispensing process, which positions the substrates 10 and moreover blocks the gaps 17 to prevent the overflow problem. Alternatively, the adhesive material 41 may be made of a polymer material such as an epoxy resin.

Second Embodiment

FIGS. 4A to 4H shows a method for fabricating semiconductor packages according to a second embodiment of the present invention, wherein the size of the substrates 10 is designed to be slightly smaller than the predefined size of the completed semiconductor packages 1 (FIG. 4H) so as to further decrease the use of substrate material, the predefined size of semiconductor packages 1 still being 31 mm×31 mm.

As shown in FIG. 4A, a build-up substrate 10 of a plurality of build-up substrates carrying a chip 20 of a plurality of chips is prepared. The build-up substrates 10 have a size of 30.8 mm×30.8 mm, which is slightly smaller than the predefined size 31 mm×31 mm of semiconductor packages 1. Then, as shown in FIG. 4B, a carrier 15 having a plurality of openings 16 is prepared. The size of the openings 16 is bigger than that of the semiconductor packages 1 such that the substrates 10 having the chips 20 can be embedded and positioned in the corresponding openings 16. In the present embodiment, the openings 16 have a size of 31.5 mm×31.5 mm. As shown in FIG. 4C, a plurality of substrates 10 is positioned in the openings 16 of the carrier 15, and the gaps 17 between the substrates 10 and the carrier 15 are blocked so as to prevent the gaps 17 form penetrating through the carrier 15. In the present embodiment, a tape 25 is attached to the lower surfaces of the substrates 10 and the carrier 15 for positioning the substrates 10 and meanwhile covering the gaps 17.

Subsequently, as described in the first embodiment, a mold press process, a mold releasing process, a tape removing process, and a ball mounting process are performed sequentially as shown in FIGS. 4D to 4F. In the present embodiment, the tape 25 can prevent overflow of the encapsulant 32, and size of the mold cavities 31, which is made to be bigger than that of the openings 16, can facilitate mold releasing. Thus, the size of the substrates 10 is also reduced through the present embodiment.

As shown in FIG. 4G, a cutting process is performed along edges of the substrates 10 according to the predefined size of the semiconductor packages 1. In the present embodiment, as the predefined size of the semiconductor packages 1 is 31 mm×31 mm and the size of the substrates 10 is 30.8 mm×30.8 mm, after the cutting process, the encapsulant 32 with a width of 0.1 mm is left at the edges of the semiconductor packages 1. Compared with the prior art of FIG. 12 that needs to leave redundant edge material with a width of 1.18 mm (0.6 mm+0.58 mm, excluding a cutting path with a width of 0.3 mm) in the substrate 70, the present embodiment greatly decreases the use of substrate material. Then, as shown in FIG. 1H, a plurality of low-cost semiconductor packages 1 is obtained.

However, the size of the substrates 10 is not limited to 30.8 mm×30.8 mm. The length and width of the substrates 10 can be 0.1 to 0.5 mm smaller than the predefined length and width of the semiconductor packages 1. Moreover, the size of the openings 16 of the carrier 15 is not limited to 31.5 mm×31.5 mm. Instead, the length and width of the openings 16 can be 0.1 to 1 mm bigger than the predefined length and width of the semiconductor packages 1. Ideally, the length and width of the openings 16 are 0.5 mm bigger than length and width of the semiconductor packages 1.

Third Embodiment

In addition to an organic material such as FR4, FR5, BT and so on, the carrier 15 may also be made of a metallic material. Therein, a metal-plated layer having poor adhesion with the encapsulant 32 is formed on a surface of the carrier 15. A method for fabricating semiconductor packages using such a metallic carrier is shown in FIGS. 5A to 5I.

As shown in FIG. 5A, a plurality of build-up substrates 10 carrying chips 20 is prepared, the size of which is designed to be 31.4 mm×31.4 mm. The predefined size of semiconductor packages 1 is 31 mm×31 mm. As shown in FIG. 5B, a substrate carrier 45 made of a metallic material such as copper is prepared, which comprises a plurality of openings 46. Therein, the carrier has a metal plated layer formed with a material such as Au, Ni or Cr. The metal plated layer has poor adhesion with the encapsulant 32. As shown in FIGS. 5C to 5E, the plurality of substrates 10 is positioned in the openings 46 of the carrier 45, and a tape 25 is used to cover the gaps 47 between the substrates 10 and the carrier 45 so as to prevent the gaps 47 from penetrating through the carrier 45; a mold press process is performed to form the encapsulants 32; and then a mold releasing process and a tape removing process are performed.

As the metallic carrier 45 has a metal plated layer with poor adhesion with the encapsulants 32, the encapsulants 32 can easily be separated from the carrier 45. As shown in FIG. 5F, the substrates 10 and the chips 20 encapsulated by the encapsulants 32 are taken out from the openings of the carrier 45, thereby obtaining a plurality of packaged units 2.

As shown in FIGS. 5G to 5I, a ball mounting process and a cutting process are performed to obtain a plurality of semiconductor packages I having predefined size. As the present embodiment separates the package units 2 from the carrier 45 first before the cutting process, the carrier 45 is prevented from being cut during the cutting process, thereby facilitating the fabrication process.

Fourth Embodiment

In the aforementioned embodiments, the encapsulants 32 formed in the mold press process also encapsulate the conductive bumps 50 (as in FIG. 6) of the chips 20 so as to complete the underfill process. Alternatively, as shown in FIG. 6, a bottom underfill material 51 made of resin, for example, can be used to encapsulate the conductive bumps 50 before the mold press process is performed, thereby ensuring and strengthening the electrical properties of the semiconductor packages 1.

Fifth Embodiment

As shown in FIG. 7, the encapsulants 32 of the semiconductor packages I can be ground so as to expose non-active surfaces 201 of the chips 20, thereby improving the heat dissipating efficiency and reducing the height of the semiconductor packages 1.

Sixth Embodiment

Alternatively, as shown in FIG. 8, a heat sink 60 is first attached to non-active surface 201 of the chip 20 and then a mold press process is performed to form the encapsulant 32, thereby improving the heat dissipating efficiency of the whole semiconductor package 1.

Seventh Embodiment

The semiconductor package 1 in FIG. 8 can also be ground so as to remove the encapsulant 32 located on the heat sink 60. Thus, the heat sink 60 is exposed from the encapsulant 32 for improving the heat dissipating efficiency, as shown in FIG. 9.

Eighth embodiment

Referring to FIGS. 13A and 13B, to quickly perform the aforementioned dispensing method for filling an adhesive material 41′, such as a solder mask or an epoxy resin, in the gaps 17′ between the substrate 10′ and the carrier 15′ so as to position the substrate 10′and block the gap 17′, the gaps 17′ should at least have a width of 1 mm such that the adhesive material 41′ can be quickly filled in the gaps 17′ through a pen-write method. However, the bigger the gaps 17′, the more the adhesive material 41′ is needed, thus increasing the cost. Moreover, gaps 17′ that are relatively large can easily lead to shift of the substrates 10′ pre-attached to the tape, which may result in trouble in the subsequent processes. For example, due to substrate shift, the size of the gaps at two opposite sides of the substrate can be different. As a result, the adhesive material filled in the gap at one side can be insufficient while the adhesive material filled in the gap at the other side overflows, as shown in FIG. 13A. After the encapsulant 32′ is formed to encapsulate the chip 20′, the overflowed adhesive material 41′ is left between the encapsulant 32′ and the substrate 10′, which can easily lead to edge delamination. On the other hand, if the gaps 17′ are too small, the substrate shift problem can be prevented. However, a substantially smaller dispensing needle is required for sufficiently filling the adhesive material 41′ in the gaps 17′, which not only slows down the dispensing speed, but also increases the fabrication costs.

Therefore, the present embodiment is proposed to overcome the above problems.

FIG. 14A is a top view of a carrier 15′ with a substrate 10′ disposed in the opening 16′of the carrier 15′. As shown in FIG. 14A, at least one (four) storage hole 150′ is formed at the periphery of the opening 16′ of the carrier 15′. In the present embodiment, the storage holes 150′ are formed at the four corner of the opening 16′ of the carrier 15′. In addition, the gaps 17′ between the substrate 10′ and the opening 16′ are about 0.05 mm to 0.2 mm in width, and preferably 0.1 mm.

As shown in FIG. 14B, an adhesive material 41′ is filled in the storage holes 150′ through a dispensing method. Then, through a capillary effect, the adhesive material 41′ of the storage holes 150′ is further flowed into the gaps 17′, as shown in FIG. 14C. Thus, the substrate 10′ is easily and efficiently positioned in the opening 16′ of the carrier 15′, and the gaps between the substrate 10′ and the carrier 15′ are effectively blocked. Moreover, as the adhesive material 41′ is filled in the gaps 17′ through the capillary effect, problems such as substrate shift, uneven distribution of adhesive material, and interface delamination caused by gaps 17′ that are too large are prevented, and also problems such as too slow of a dispensing speed and increased fabrication cost caused by gaps 17′ that are too small are avoided.

The carrier 15′ may be made of an organic dielectric material selected from the group consisting of FR4, FR5, and BT. The mold press process, the mold releasing process, and the cutting process can then be performed as mentioned above so as to obtain completed semiconductor packages. Alternatively, the carrier 15′ can be made of a metallic material. Referring to the aforementioned embodiment, the mold press process, the mold releasing process, the carrier separating process, and the cutting process can then be performed so as to obtain completed semiconductor packages.

Referring to FIG. 15A, the storage holes (two storage holes) 150′ can further be disposed at two corner instead of four corner of the openings 16′, or, as shown in FIG. 15B, at least one storage hole 150′ can be disposed at each of the four sides of the opening 16′. Alternately, as shown in FIG. 15C, two or more storage holes 150′ can be disposed at two or more sides of the opening 16′, thus allowing the adhesive material 41′ of the storage holes 150′ to be sufficiently filled in the gaps 17′ through the capillary effect.

The present invention also discloses a method for positioning a semiconductor component, which comprises: providing a semiconductor component and a carrier, wherein, the semiconductor component can be, for example, a substrate 10′ and the carrier 15′ has an opening 16′, the length and width of the opening 16′ being bigger than the length and width of the semiconductor component, and at least one storage hole 150′ being disposed at the periphery of the opening 16′ of the carrier 15′; and disposing the semiconductor component in the opening 16′ of the carrier 15′, and also performing a dispensing process in the storage hole 150′ so as to fill an adhesive material 41′ into the storage hole 150′, wherein the adhesive material 41′ then flows into the gaps 17′ between the semiconductor component and the carrier 15′ by capillary action, thereby positioning the semiconductor component in the carrier 15′.

The present invention further discloses a carrier structure for positioning a semiconductor component, which comprises: a carrier 15′ having an opening 16′ for receiving the semiconductor component; and at least a storage hole 150′ disposed at the periphery of the opening 16′ of the carrier 15′ such that an adhesive material can be filled in the storage hole 150′, which then, through the capillary effect, flows into the gaps between the semiconductor component and the carrier 15′, thereby positioning the semiconductor component in the carrier 15′. The semiconductor component can be, for example, a substrate 10′.

Although the above-described embodiments are slightly different in fabrication methods or selected materials, they have the same characteristics. That is, the length and width of the prepared substrates 10, 10′ are approximately equal to the predefined length and width of semiconductor packages 1. As the gaps 17, 47, 17′ between the substrates 10, 10′ and the carriers 15, 45, 15′ are all blocked, and meanwhile, the projection length and width of the mold cavities 31 for forming the encapsulants 32 are bigger than the length and width of the openings 16, 46, 16′, the overflow problem is overcome and the mold releasing process is facilitated, which thus eliminates the need for increasing the size of the substrates 10, 10′, thereby reducing the material costs and facilitating the fabrication process.

It should be noted that the electrical connecting method of the chips is not limited by the present invention. Instead of using a flip chip method, the chips can also be electrically connected to the substrates through a wire bonding method.

The present invention also discloses a method for positioning a semiconductor component such as a substrate in a carrier while blocking the gaps between the semiconductor component and the carrier, which comprises the step of filling an adhesive material in the storage holes disposed at the periphery of the opening of the carrier. Through the capillary effect, the adhesive material is further filled in the gaps between the semiconductor component and the carrier. Thus, the semiconductor component is simply positioned in the opening of the carrier. As the adhesive material is filled in the gaps through the capillary effect, problems such as semiconductor component shift, uneven adhesive material distribution, and interface delamination caused by gaps that are too large can be prevented. Moreover, such problems as too slow of a dispensing speed and increased fabrication costs caused by gaps that are too small can also be avoided.

The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and are not intended to limit the scope of the present invention. Accordingly, various modifications and variations made by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims. 

1. A method for fabricating semiconductor packages, comprising the steps of: preparing a plurality of substrates and a carrier having a plurality of openings, wherein, each of the substrates has at least one chip disposed thereon, the length and width of the substrates are close to the predefined length and width of the semiconductor packages, and the length and width of the openings of the carrier are bigger than the length and width of the substrates; respectively positioning the substrates in the openings of the carrier and blocking the gaps between the substrates and the carrier so as to prevent the gaps from penetrating through the carrier; performing a mold press process so as to form an encapsulant on each of the openings for encapsulating the chip, wherein the length and width of the area covered by each encapsulant are bigger than length and width of each opening; performing a mold releasing process; and cutting along edges of the substrates according to the predefined length and width of the semiconductor packages, thereby obtaining a plurality of semiconductor packages.
 2. The method of claim 1 further comprising the step of mounting a plurality of solder balls on surfaces of the substrates without chips disposed thereon after the mold releasing process is performed.
 3. The method of claim 1, wherein the projection length and width of the mold cavities for forming the encapsulants are bigger than length and width of the openings.
 4. The method of claim 1, wherein an adhesive material is filled in the gaps between the substrates and the carrier so as to position the substrates in the openings.
 5. The method of claim 1, wherein at least one tape is attached to the substrates and the carrier, covering the openings and positioning the substrates in the openings, the tape being removable after the mold releasing process.
 6. The method of claim 1, wherein an adhesive material is filled in the gaps between the substrates and the carrier so as to block the gaps.
 7. The method of claim 1, wherein at least one tape is attached to the substrates and the carrier for blocking the gaps between the substrates and the carrier, the tape being removable after the mold releasing process.
 8. The method of claim 1, wherein the length and width of the substrates are 0.1 to 0.5 mm bigger than the predefined length and width of the semiconductor packages.
 9. The method of claim 1, wherein, when the length and width of the substrates are 0.1 to 0.5 mm bigger than the predefined length and width of the semiconductor packages, the length and width of the openings are 0.1 to 0.5 mm bigger than length and width of the substrates.
 10. The method of claim 1, wherein the length and width of the substrates are 0.1 to 0.5 mm smaller than the predefined length and width of the semiconductor packages.
 11. The method of claim 1, wherein, when the length and width of the substrates are 0.1 to 0.5 mm smaller than the predefined length and width of the semiconductor packages, the length and width of the openings are 0.1 to 1 mm bigger than the predefined length and width of the semiconductor packages.
 12. The method of claim 1, wherein the carrier is made of an organic dielectric material selected from the group consisting of FR4, FR5 and BT.
 13. The method of claim 1, wherein the chips are partially exposed from the encapsulants.
 14. The method of claim 1, wherein heat sinks are disposed on surfaces of the chips opposed to the substrates.
 15. The method of claim 14, wherein the heat sinks are partially exposed from the encapsulants.
 16. The method of claim 1, wherein the chips are electrically connected to the substrates through a flip-chip method.
 17. The method of claim 1, wherein the chips are electrically connected to the substrates through a wire bonding method.
 18. The method of claim 1, wherein the semiconductor packages are BGA semiconductor packages.
 19. A method for fabricating semiconductor packages, comprising the steps of: preparing a plurality of substrates and a metallic carrier having a plurality of openings, wherein, each of the substrates has at least one chip disposed thereon, the length and width of the substrates are close to the predefined length and width of the semiconductor packages, and the length and width of the openings of the carrier are bigger than the length and width of the substrates; respectively positioning the substrates in the openings of the metallic carrier and blocking the gaps between the substrates and the metallic carrier so as to prevent the gaps from penetrating through the metallic carrier; performing a mold press process so as to form an encapsulant on each of the openings for encapsulating the chip, thus forming a packaged unit comprising the substrate, chip, and encapsulant, wherein the length and width of the area covered by the encapsulant are bigger than length and width of the opening; performing a mold releasing process; separating the package units from the metallic carrier; and cutting along edges of the substrates of the package units according to the predefined length and width of semiconductor packages, thereby obtaining a plurality of semiconductor packages.
 20. The method of claim 19, wherein the metallic carrier is made of Cu.
 21. The method of claim 19, wherein a metal plated layer having poor adhesion with the encapsulant is formed on the metallic carrier.
 22. The method of claim 21, wherein the metal plated layer is one of the group consisting of Au, Ni and Cr.
 23. The method of claim 19, further comprising the step of mounting a plurality of solder balls on surfaces of the substrates without chips disposed thereon after the mold releasing process is performed.
 24. The method of claim 19, wherein the projection length and width of the mold cavities for forming the encapsulants is larger than the length and width of the openings.
 25. The method of claim 19, wherein an adhesive material is filled in the gaps between the substrates and the carrier so as to position the substrates in the openings.
 26. The method of claim 19, wherein at least one tape is attached to the substrates and the carrier, covering the openings and positioning the substrates in the openings, the tape being removable after the mold releasing process.
 27. The method of claim 19, wherein an adhesive material is filled in the gaps between the substrates and the carrier so as to block the gaps.
 28. The method of claim 19, wherein at least one tape is attached to the substrates and the carrier for blocking the gaps between the substrates and the carrier, the tape being removable after the mold releasing process.
 29. The method of claim 19, wherein length and width of the substrates are 0.1 to 0.5 mm bigger than the predefined length and width of the semiconductor packages.
 30. The method of claim 19, wherein, when length and width of the substrates are 0.1 to 0.5 mm bigger than predefined length and width of the semiconductor packages, the length and width of the openings are 0.1 to 0.5 mm bigger than length and width of the substrates.
 31. The method of claim 19, wherein the length and width of the substrates are 0.1 to 0.5 mm smaller than predefined length and width of the semiconductor packages.
 32. The method of claim 19, wherein, when length and width of the substrates are 0.1 to 0.5 mm smaller than predefined length and width of the semiconductor packages, the length and width of the openings are 0.1 to 1 mm bigger than predefined length and width of the semiconductor packages.
 33. The method of claim 19, wherein the chips are partially exposed from the encapsulants.
 34. The method of claim 19, wherein heat sinks are disposed on surfaces of the chips opposed to the substrates.
 35. The method of claim 34, wherein the heat sinks are partially exposed from the encapsulants.
 36. The method of claim 19, wherein the chips are electrically connected to the substrates through a flip-chip method.
 37. The method of claim 19, wherein the chips are electrically connected to the substrates through a wire bonding method.
 38. The method of claim 19, wherein the semiconductor packages are BGA semiconductor packages.
 39. A method for fabricating semiconductor packages, the method comprising: providing a plurality of substrates and a carrier having a plurality of openings, each of the substrates having at least one chip disposed thereon, a substrate length and width approximately equal to a predefined length and width of each of the semiconductor packages, each of the openings of the carrier having an opening length and width larger than the substrate length and width of the each of the substrates, at least a storage hole being formed at a periphery of one of the openings of the carrier; positioning the substrates in the openings of the carrier respectively and filling into the storage hole an adhesive material, which flows in gaps between the substrates and the carrier through a capillary effect; forming encapsulant on the openings to encapsulate the chips, area where the encapsulant is formed on each of the openings being larger than the opening length and width of the opening; performing a mold releasing process; and cutting along edges of the substrates according to the predefined length and width of the semiconductor packages, thereby obtaining the semiconductor packages.
 40. The method of claim 39 further comprising mounting a plurality of solder balls on the substrates where the chips are not disposed after the mold releasing process is performed.
 41. The method of claim 39 further comprising providing a plurality of mold cavities, for forming the encapsulant, each of the mold cavities having a projection length and width larger than the opening length and width of each of the openings.
 42. The method of claim 39 further comprising attaching at least one tape to the substrates and the carrier, for covering the openings and positioning the substrates in the openings, and removing the tape after the mold releasing process.
 43. The method of claim 39, wherein at least one of the gaps is 0.05 to 0.2 mm in width.
 44. The method of claim 43, wherein the at least one of the gaps is 0.1 mm in width.
 45. The method of claim 39, wherein the carrier is made of an organic dielectric material selected from the group consisting of FR4, FR5 and BT.
 46. The method of claim 39, wherein the carrier is made of a metallic material.
 47. The method of claim 39, wherein the storage hole is disposed at a corner of each of the openings of the carrier.
 48. The method of claim 39, wherein the storage hole is disposed at a side of each of the openings of the carrier.
 49. A method for positioning a semiconductor component, the method comprising: providing a semiconductor component and a carrier having an opening having an opening length and width larger than a semiconductor length and width of the semiconductor component; disposing at least one storage hole at a periphery of the opening of the carrier; disposing the semiconductor component in the opening of the carrier; and filling into the storage hole an adhesive material, which is filled in gaps between the semiconductor component and the carrier through a capillary effect, thereby positioning the semiconductor component in the carrier.
 50. The method of claim 49, wherein at least one of the gaps is 0.05 to 0.2 mm in width.
 51. The method of claim 50, wherein the gap is 0.1 mm in width.
 52. The method of claim 49, wherein the storage hole is disposed at a corner of the opening of the carrier.
 53. The method of claim 49, wherein the storage hole is disposed at a side of the opening of the carrier.
 54. A carrier structure for positioning a semiconductor component, the carrier structure comprising: a carrier having an opening for receiving the semiconductor component; and at least a storage hole disposed at a periphery of the opening of the carrier, for an adhesive material to be filled in, the adhesive material, through the capillary effect, being filled in gaps between the semiconductor component and the carrier, thereby positioning the semiconductor component in the carrier.
 55. The carrier structure of claim 54, wherein at least one of the gaps is 0.05 to 0.2 mm in width.
 56. The carrier structure of claim 55, wherein the gap is 0.1 mm in width.
 57. The carrier structure of claim 54, wherein the storage hole is disposed at a corner of the opening of the carrier.
 58. The carrier structure of claim 54, wherein the storage hole is disposed at a side of the opening of the carrier. 